In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form circuits. Interconnection of these devices within an integrated circuit is typically accomplished by forming a multi-level interconnect network in layers formed over the electrical devices, by which the device active elements are connected to other devices to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching contact openings such as vias. Conductive material, such as tungsten is then deposited into the vias to form inter-layer contacts. A conductive layer may then be formed over the dielectric layer and patterned to form wiring interconnections between the device vias, thereby creating a first level of basic circuitry. Dielectric material is then deposited over the patterned conductive layer, and the process may be repeated any number of times using additional wiring levels laid out over additional dielectric layers with conductive vias therebetween to form the multi-level interconnect network.
As device densities and operational speeds continue to increase and transistor scaling proceeds into the deep sub-micron regime, reduction of the delay times in integrated circuits is desired. These delays are related to the resistance of interconnect metal lines through the multi-layer interconnect networks as well as the parasitic capacitance between adjacent metal lines. Recent interconnect processes have employed copper instead of aluminum, in order to reduce the resistivity of the interconnect metal lines which are formed in metal layers or structures. However, difficulties have been encountered in patterning (e.g., etching) deposited copper to form wiring patterns. Furthermore, copper diffuses rapidly in certain types of insulation/dielectric layers, such as silicon dioxide, leading to insulation degradation and/or copper diffusion through the insulation layers and into device regions.
Copper patterning difficulties have been avoided or mitigated through the use of single or dual damascene processes in which trenches are formed (etched) in a dielectric layer. A thin diffusion barrier (e.g., tantalum nitride) is deposited which “lines” the dual damascene trench and via over the insulative layers. Copper is then deposited into the trenches over the barrier layer, followed by planarization using a chemical mechanical polishing (CMP) process to leave a copper wiring pattern including the desired interconnect metal lines inlaid within the dielectric layer trenches and vias. In a single damascene process copper trench patterns are thus created which connect to pre-existing underlying vias, whereas in a dual damascene process, both vias and the trenches are filled at the same time using single copper deposition and CMP steps.
Copper diffusion issues have been addressed using copper diffusion barriers formed between the copper and the dielectric layers as well as between the copper and the silicon substrate. Such barriers are typically formed using conductive compounds of transition metals such as tantalum, tantalum nitride, tantalum silicon nitride, PVD tantalum, titanium nitride, and tungsten nitride as well as the various transition metals themselves. Insulators such as silicon nitride and silicon oxynitride have also been used as barrier materials between copper metallurgy and insulative layers. More recently, silicon carbide (SiC) has been used as a copper diffusion barrier material, as well as etch-stop layers and hard masks used during trench and/or via cavity formation.
RC delay times have also been addressed by recent developments in porous low dielectric constant (low-k) dielectric materials formed between the wiring metal lines, in order to reduce the capacitance therebetween and consequently to increase circuit speed. Examples of low-k dielectric materials include the spin-on-glasses (SOGs), as well as organic and quasi-organic materials such as polysilsesquioxanes, fluorinated silica glasses (FSGs) and fluorinated polyarylene ethers. Organic, non silicaceous materials such as the fluorinated polyarylene ethers are seeing an increased usage in semiconductor processing technology because of their favorable dielectric characteristics and ease of application. Other low-k insulator materials include organo-silicate-glasses (OSGs), for example, having dielectric constants (k) as low as about 2.6-2.8, and ultra low-k dielectrics having dielectric constants below 2.5. OSG materials are low density silicate glasses to which alkyl groups have been added to achieve a low-k dielectric characteristic.
Single and dual damascene processes using OSG, FSG, a low-k dielectric or ultra low-k dielectric materials, SiC and SiC:H materials, and copper metals can thus be employed to increase speed, reduce cross-talk, and reduce power consumption in modern high-speed, high-density devices.
Either the trench level or the via level can be etched first to form a dual damascene interconnect. The first approach has greater worst case misalignment error to the underlying level as compared to the via first approach. Both approaches require resist patterning over topography, reducing photolithography process margin.
Generally inherent to the dual damascene approach is two dielectric layers, the IDL (inter-level dielectric) and the IMD (intra-metal dielectric), which are typically separated by an embedded etch stop layer (e.g., SiN, or the newer SiC:H). In the via-first approach, the embedded etch stop layer serves as an etch stop for the trench etch, and is therefore also referred to as a “trench e-stop layer” (TES). The trench e-stop layer TES is sometimes also be referred to as a “buried via mask”, as this layer takes on a dual role. The TES layer continues to provide a trench e-stop function, but also provides a mask function to aid forming the lower via to the underlying metal level lines (or other such conductive features) of the M1 metal layer. However, in a conventional approach, openings in the buried via mask were aligned to the long axis of the underlying metal lines. This on-axis alignment, however, tends to somewhat limit the margin of error allowable between a metal line and the resultant conductive interconnect between the metal levels, because the width of these via mask openings may still limit the interconnect contact area in some instances.
Further, as metal lines and interconnects are scaled down into sub-micron widths, alignment error margins also critically reduce between the various metal level lines and the conductive interconnects connecting the metal levels. Thus, the masks which guide the etching of these interconnects also provide an increasingly important role, while alignment error margins are reduced as features continue to crowd together.
FIGS. 1A-1D, for example, illustrate a partial plan view and a partial cross sectional view of a conventional approach of forming a conductive interconnect between two metal lines (conductive features) at two respective metal levels M1 and M2. FIGS. 1A-1C illustrate ideal alignment between the metal lines, and the interconnect formed therebetween, while FIG. 1D illustrates a worst case misalignment error situation between the conductive features and the interconnect. While FIGS. 1C and 1D only show the interconnect cavity which is formed between the M1 and the M2 metal levels, it is understood that a subsequent method step typically deposits a conductive interconnect material within the cavity. In addition, a diffusion barrier layer is commonly deposited before a copper conductive interconnect material is deposited in the interconnect cavity to act as a sidewall diffusion barrier.
FIGS. 1A-1D illustrate a conventional implementation, wherein an interconnect comprising a via and a trench is formed in a semiconductor device for connecting a conductive feature in a first level to a feature associated with a second level. The illustrated portions of the interconnect process involve the use of inter-level dielectrics, a hard mask and trench etch-stop layers for use in forming vias to be filled with copper.
In FIG. 1A, a semiconductor device 100 is illustrated at an intermediate stage of fabrication processing, wherein one or more electrical devices (e.g., transistors, memory cells, etc., not shown) have been formed on or in a substrate 104, such as silicon. In order to interconnect such devices, and/or to provide external connections thereto, interconnect processing is employed to fabricate one or more levels of copper connection metal lines for forming a desired circuit. Copper-filled vias are formed to vertically provide electrical connections from one such level to another, wherein insulative dielectric material is formed between such trenches and vias to isolate unconnected conductive features from one another.
A conductive feature 106 is formed within an opening in a metal dielectric material 105 of a first metal layer (M1) over the substrate 104 in FIG. 1A, and a first diffusion barrier layer (B1) 108 is formed over the conductive feature 106 typically when the M1 conductive feature 106 comprises copper, wherein the via is provided to connect the conductive feature 106 to a first interconnect level. An first inter-level dielectric layer (ILD1) 110 is formed over the B1 first diffusion barrier layer 108. The ILD1 first inter-level dielectric layer 110 provides insulation between overlying and underlying conductive features and relatively low dielectric constant characteristics are desirable in avoiding or mitigating RC delays and cross-talk between signals in the finished integrated circuit of the device 100.
A trench etch-stop layer (TES) 111 is deposited over the ILD1 layer 110, and a via opening 111′ may be etched in the trench etch-stop layer TES 111 as shown in both plan and cross sectional views of FIG. 1A. In the dual damascene process, the TES layer 111 may be covered by overlying layers, and thus may also be referred to as an “embedded trench etch-stop layer” 111, or a “buried via mask” 111. The trench etch-stop layer (TES) 111 provides a stopping point for etching of an overlying trench and the via opening 111′ provides a mask for the further etching of the via underlying the trench etch-stop layer.
Thereafter in FIG. 1B, a second inter-level dielectric layer (ILD2) 112 is formed over the TES layer 111, a hard mask layer (HM) 114 is formed over ILD2 layer 112, and an M2 second metal layer opening 114′ (for the later formation of an M2 conductive feature) may be etched in the HM layer 114 as shown in both plan and cross sectional views of FIG. 1B. The HM layer 114 is typically used in trench formation in a dual damascene type interconnect process while forming overlying trenches for interconnection of copper metal lines with vias formed through the ILD1 layer 110.
In FIG. 1C, a first etch process 122 is then performed through the openings 114′ in the HM layer 114 to remove the exposed portions of the ILD2 layer 112, leaving a trench cavity 116. The etch process 122 continues by removing the exposed portion of the ILD1 layer 110 and the B1 layer 108 through the buried via mask of the TES layer 111, leaving a via cavity 118, and an exposed portion of the conductive feature 106 in the M1 metal layer. Therefore, a trench (cavity) may be formed above the TES layer 111, and a via (cavity) formed below the TES layer 111, collectively forming an interconnect cavity. The interconnect cavity may then be filled to form a conductive interconnect to connect the M1 and M2 conductive features.
FIGS. 1A-1C further demonstrates, that when an ideal alignment is achieved between the M1 and M2 metal layer conductive features and the via mask opening 111′, a conductive interconnect may be formed therebetween providing a full contact area 120 in the conventional method. However, as was discussed, ideal alignment is difficult as the increased densities and sub-micron conductor trends continue.
FIG. 1D illustrates an alignment problem with a conventional method approach. The M1 and the M2 metal layer conductive features, and the via mask opening 111′ are shown placed in worst-case misalignment positions. A positioning error 123 resulting from an offset 124 in the position of the via mask opening causes a reduced contact area 120′ for the conductive interconnect which may produce increased contact resistance, power consumption, and increased photo re-work at via and trench levels.
In addition, incorporating these newer materials and process methods into workable semiconductor fabrication processes presents additional challenges. Among these are the formation of damascene structures, including vias and trenches. In particular, it is desirable to provide self-aligned formation of vias and trenches through the dielectric layers accomplished in a single etch operation with increased alignment error margins between corresponding metal level features to properly interconnect electrical devices such as transistors, memory cells, and the like to limit power consumption and to take advantage of the potential performance benefits of such newer interconnect network materials and process methods.